After being fabricated, integrated circuits (ICs) are tested for proper functional operation using a set of test vectors that contain test inputs and the expected test outputs. Test vectors generated by Automatic Test Pattern Generation (ATPG) software are applied to the chip or device under test (DUT) by an Automatic Test Equipment (ATE). The ICs that successfully passed all the test vectors are qualified as good whereas the ICs that failed on any of the test vectors are qualified as bad or defective. For the defective ICs, the failure information is collected by the ATE and stored in a buffer for further processing using diagnostics tools.
To achieve high fault coverage with low pattern count and facilitate ease of testing the integrated circuit (IC), test methodology is designed and implemented with multiple test configurations. Each configuration activates specific logic in the circuit and patterns are generated specific to the configuration. Debugging issues and reporting information across multiple test configurations is critical to determine the quality of results at the full chip level. FIG. 1 shows the process flow for testing different configurations. In a single session, single test configuration related information is processed by the tool. Once the information for all interested test configurations is available, the user post processes the information available in log files or any tool-supported techniques to collect the final results. This data is obtained by parsing through log files or through creation of custom scripts.
There are challenges with the aforementioned approach. First, a special set-up is established to post-process the information collected from various sessions. Second, navigation and interactive debug of information across multiple test configurations are not available. This data is required for continuous assessment of quality of results at the chip level. Third, a scripted environment to explore multiple test configurations is challenging in this structure.